Reducing SRAM Power Lose For POR Using H-SPICE

Design of a low-energy power-ON reset (POR) circuit is proposed to reduce the energy consumed by the stable supply of the dual supply static random access memory (SRAM), as the other supply is ramping up. The proposed POR circuit, when embedded inside dual supply SRAM, removes its ramp-up constraints related to voltage sequencing and pin states. The proposed design is modified version of exiting circuit POR-LE (low energy power-on-reset) where additional transistor NSLOW and PFAST removes from the network that reduces standby power dissipation of the design as well as reduces circuit complexity. Two additional transistors added in push-pull output stage in forced stack topology to reduce the overall energy consumption of the proposed design. Proposed design offers 0.1735┬Ás delay which is 8.2% lower than POR-LE while offers 1.2% higher power dissipation than POR-LE. But the multiplication of power and delay (is also called energy) is 7% smaller than POR-LE. The normalized comparison of various Normalized design parameter used for POR circuit design are shown in Fig.

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